1. Field of the Invention
This invention is related to the field of signal transmission paths and, more particularly, to diagnosing interconnect faults.
2. Description of the Related Art
Computing systems and components typically have numerous communication paths which must remain operable for the system as a whole to operate correctly. Such communication paths occur within given assemblies (e.g., a single printed circuit board, device, or chip), and across such assemblies as well. For example, multiple boards may be coupled to communicate via connectors. When an error is detected, identifying the location of a fault can be quite difficult. A fault could be due to a short, a failure of a trace line, a faulty connector, and so on. Often times, a service engineer may not be able to isolate the location of such a fault and may simply attempt to correct the problem via trial and error. For example, the engineer may first replace an entire printed circuit board. After replacing the board, further tests may be run to determine whether the fault has been corrected. If the fault has not been corrected, further testing must generally be performed. As may be appreciated, such an approach is fairly inefficient, costly, and may lead to increased downtime for a customer. In addition to the above, systems and assemblies are typically tested prior to being approved for distribution or sale. During such testing, it is similarly desirable that the location of a given fault be identified in an efficient and cost effective manner.
FIG. 1 depicts one embodiment of a system 100 which includes a variety of components and multiple communication paths, or channels. In the example shown, system 100 includes a printed circuit board (or device package) 110 which includes a chip or board 120. Chip 120 may, for example, be mounted upon board 110. In such a case, there may exist an interface 122 between the chip 120 and the board 110. In addition, or alternatively, chip 120 may comprise a packaged device manufactured to include a ball grid array, or any other suitable technology. Also illustrated is a device 130 which is not located directly on the board 110. Alternatives emodiments may include both of devices 130 and 140 on a single card or board. Device 130 is coupled to communicate with chip 120 via signal lines 112 and 114. Signal lines 112 and 114 may comprise PCB traces, or any other suitable transmission paths. In the embodiment shown, device 130 connects to board 110 via a connector 180. Through the connector 180, the device 130 is able to communication with the device 120.
Should the system 100 fail, or otherwise indicate an error, a fault in communication within the system 100 may be the cause. Unfortunately, determining a location of the fault may be very difficult. The fault could reside within device 130, or within device 120. Alternatively, a defect may exists in one of the signal line 112 or 114 between device 130 and connector 180. Further, the fault may exist within the connector 180, or between the connector 180 and the device 120. Still further, a fault may exist in a solder joint 122 which connects device 120 to board 130. Consequently, while it may be possible to determine that a problem exists, the location of a given fault cannot be determined without additional information. In some cases, the determination as to where a fault may exist is based upon past experience, or probabilities. However, such approaches do not provide any certainty.
Accordingly, a method and mechanism for determining a location of a fault in a transmission path is desired.